[External] Re: Current status of RISC-V init_cache_level()

[yunhui cui]

Hi Conor,

On Fri, Jan 19, 2024 at 4:59 PM yunhui cui <cuiyunhui at bytedance.com> wrote:
>
> Hi Conor，
>
> On Fri, Jan 19, 2024 at 4:22 PM Conor Dooley <conor.dooley at microchip.com> wrote:
> >
> > On Fri, Jan 19, 2024 at 10:32:38AM +0800, yunhui cui wrote:
> > > On Thu, Jan 18, 2024 at 9:25 PM Conor Dooley <conor at kernel.org> wrote:
> > > > On Thu, Jan 18, 2024 at 07:40:42PM +0800, yunhui cui wrote:
> > > >
> > > > Firstly, please don't send me off-list mails about such things
> > > > and instead, please reply to the relevant threads on lkml.
> > > >
> > > > > There is no cache subdirectory in /sys/devices/system/cpu/cpu0/, so
> > > > > lscpu cannot see the cache information. I found that the reason is
> > > > > that init_cache_level() is not implemented on RISC-V.
> > > >
> > > > What version of the kernel are you using? I had a brief check to make
> > > > sure something had not gone awry recently and I could see them on my
> > > > system. What do the cpu nodes in your DT look like, assuming you are
> > > > on a DT system?
> > >
> > > The results of top commit using linux-next on qemu, It should not
> > > matter if it is combined with DT, because the following function flow
> > > directly fails.
> >
> > Oh no, it totally does matter what the DT looks like. The default DT in
> > QEMU's virt machine does not populate any cache properties. On a system
> > where the DT populates these values, init_of_cache_level() will ensure
> > that the correct sysfs entries are set up.
> >
> > > cacheinfo_sysfs_init()...init_cache_level()
> > > int __weak init_cache_level(unsigned int cpu)
> > > {
> > > return -ENOENT;
> > > }
> > > Is it necessary to implement an init_cache_level() on RISC-V like other arches?
> >
> > In order to implement that function, we would need some mechanism for
> > finding that information. Where do you suggest we get it from, if it is not
> > provided to us from DT?
>
> It's not that we don't get cache information from DT. What I want to
> express is that we need to implement init_cache_level() on RISC-V,
> otherwise cacheinfo_cpu_online() will return from
> detect_cache_attributes() and will not execute cache_add_dev(), so it
> will not be in/ sys/devices/system/cpu/cpux/ creates a "cache" node.

What do you think? If so, I will post a patch to fix it.

Thanks,
Yunhui