[v10, 00/10] riscv: support kernel-mode Vector

[Lad, Prabhakar]

Hi Andy,

On Sat, Jan 13, 2024 at 1:26 PM Andy Chiu <andy.chiu at sifive.com> wrote:
>
> Hi Prabhakar,
>
> On Sat, Jan 13, 2024 at 4:05 AM Lad, Prabhakar
> <prabhakar.csengg at gmail.com> wrote:
> >
> > On Fri, Jan 12, 2024 at 6:32 AM <patchwork-bot+linux-riscv at kernel.org> wrote:
> > >
> > > Hello:
> > >
> > > This series was applied to riscv/linux.git (for-next)
> > > by Palmer Dabbelt <palmer at rivosinc.com>:
> > >
> > > On Thu, 11 Jan 2024 13:15:48 +0000 you wrote:
> > > > This series provides support running Vector in kernel mode.
> > > > Additionally, kernel-mode Vector can be configured to run without
> > > > turnning off preemption on a CONFIG_PREEMPT kernel. Along with the
> > > > suport, we add Vector optimized copy_{to,from}_user. And provide a
> > > > simple threshold to decide when to run the vectorized functions.
> > > >
> > > > We decided to drop vectorized memcpy/memset/memmove for the moment due
> > > > to the concern of memory side-effect in kernel_vector_begin(). The
> > > > detailed description can be found at v9[1]
> > > >
> > > > [...]
> > >
> > > Here is the summary with links:
> > >   - [v10,01/10] riscv: Add support for kernel mode vector
> > >     https://git.kernel.org/riscv/c/c0ae350f714f
> > >   - [v10,02/10] riscv: vector: make Vector always available for softirq context
> > >     https://git.kernel.org/riscv/c/ebf52ac30e4f
> > >   - [v10,03/10] riscv: Add vector extension XOR implementation
> > >     https://git.kernel.org/riscv/c/9ff97211a623
> > >   - [v10,04/10] riscv: sched: defer restoring Vector context for user
> > >     https://git.kernel.org/riscv/c/f4471252f3b9
> > >   - [v10,05/10] riscv: lib: vectorize copy_to_user/copy_from_user
> > >     https://git.kernel.org/riscv/c/145ca6eddd70
> > >   - [v10,06/10] riscv: fpu: drop SR_SD bit checking
> > >     https://git.kernel.org/riscv/c/25a830944773
> > >   - [v10,07/10] riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}()
> > >     https://git.kernel.org/riscv/c/9dece8bf0343
> > >   - [v10,08/10] riscv: vector: use a mask to write vstate_ctrl
> > >     https://git.kernel.org/riscv/c/c05992747c96
> > >   - [v10,09/10] riscv: vector: use kmem_cache to manage vector context
> > >     https://git.kernel.org/riscv/c/660217429614
> > >   - [v10,10/10] riscv: vector: allow kernel-mode Vector with preemption
> > >     https://git.kernel.org/riscv/c/aa23c6172d33
> > >
> > With this series merged in RZ/Five stops booting [0], I dont get any
> > panic as such but it's a kernel freeze. Reverting this series all
> > boots up OK.
> >
> > [0] https://paste.debian.net/hidden/a8293240/
>
> Thanks for the note.
>
> Unfortunately I didn't find a direct clue of failure from your log.
> But I believe this is the same case as the alpine one above, because
> they would fail very early. I have updated a branch here[0]. It should
> be fixed now. Also, it should fix the boot failure that appears on
> Ubuntu. It would be nice if you could have a try. I will send it out
> as v11 if no further issue is detected before the week ends.
>
> [0] https://github.com/sifive/riscv-linux/tree/2b25df2ad3a3651bc1f77fec65c95a1ae656d675
>
I can confirm with the patches applied from above link, the RZ/Five
SMARC platform can boot as normal.

Cheers,
Prabhakar

> >
> > Cheers,
> > Prabhakar
> >
> > > You are awesome, thank you!
> > > --
> > > Deet-doot-dot, I am a bot.
> > > https://korg.docs.kernel.org/patchwork/pwbot.html
> > >
> > >
> > >
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>
> Thanks,
> Andy