[v11, 00/10] riscv: support kernel-mode Vector
Björn Töpel
bjorn at kernel.org
Sun Jan 14 23:16:06 PST 2024
Hi Andy,
On Mon, 15 Jan 2024 at 06:59, Andy Chiu <andy.chiu at sifive.com> wrote:
>
> This series provides support running Vector in kernel mode.
> Additionally, kernel-mode Vector can be configured to run without
> turnning off preemption on a CONFIG_PREEMPT kernel. Along with the
> suport, we add Vector optimized copy_{to,from}_user. And provide a
> simple threshold to decide when to run the vectorized functions.
[...]
> Changelog v11:
> - This is a quick respin to address boot failing on ubuntu and alpine.
> - Pass the updated copy size when calling scalar fallback.
> - Skip some bytes for scalar fallback when fauting at vse8.v with a
> non-zero $vstart. (Guo)
> - Guard riscv_v_setup_ctx_cache() with has_vector() check.
For convenience, here's the complete diff from v10:
--8<--
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index f9769703fd39..6727d1d3b8f2 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -53,6 +53,9 @@ int riscv_v_setup_vsize(void)
void __init riscv_v_setup_ctx_cache(void)
{
+ if (!has_vector())
+ return;
+
riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx",
riscv_v_vsize, 16, SLAB_PANIC,
0, riscv_v_vsize, NULL);
diff --git a/arch/riscv/lib/riscv_v_helpers.c b/arch/riscv/lib/riscv_v_helpers.c
index 6cac8f4e69e9..be38a93cedae 100644
--- a/arch/riscv/lib/riscv_v_helpers.c
+++ b/arch/riscv/lib/riscv_v_helpers.c
@@ -33,6 +33,7 @@ asmlinkage int enter_vector_usercopy(void *dst, void
*src, size_t n)
copied = n - remain;
dst += copied;
src += copied;
+ n = remain;
goto fallback;
}
diff --git a/arch/riscv/lib/uaccess_vector.S b/arch/riscv/lib/uaccess_vector.S
index 566739f6331a..51ab5588e9ff 100644
--- a/arch/riscv/lib/uaccess_vector.S
+++ b/arch/riscv/lib/uaccess_vector.S
@@ -23,22 +23,31 @@
SYM_FUNC_START(__asm_vector_usercopy)
/* Enable access to user memory */
- li t6, SR_SUM
- csrs CSR_STATUS, t6
+ li t6, SR_SUM
+ csrs CSR_STATUS, t6
loop:
vsetvli iVL, iNum, e8, ELEM_LMUL_SETTING, ta, ma
fixup vle8.v vData, (pSrc), 10f
- fixup vse8.v vData, (pDst), 10f
sub iNum, iNum, iVL
add pSrc, pSrc, iVL
+ fixup vse8.v vData, (pDst), 11f
add pDst, pDst, iVL
bnez iNum, loop
- /* Exception fixup code. It's the same as normal exit */
+ /* Exception fixup for vector load is shared with normal exit */
10:
/* Disable access to user memory */
csrc CSR_STATUS, t6
mv a0, iNum
ret
+
+ /* Exception fixup code for vector store. */
+11:
+ /* Undo the subtraction after vle8.v */
+ add iNum, iNum, iVL
+ /* Make sure the scalar fallback skip already processed bytes */
+ csrr t2, CSR_VSTART
+ sub iNum, iNum, t2
+ j 10b
SYM_FUNC_END(__asm_vector_usercopy)
--8<--
One nit that sticks out is the assembly alignment for
__asm_vector_usercopy, where tab/notab layouts are mixed.
I'll kick off a full build/boot with the v11!
Cheers,
Björn
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