[PATCH v4 01/12] riscv: Flush the instruction cache during SMP bringup

[Alexandre Ghiti]

Hi Samuel,

On Tue, Jan 2, 2024 at 11:01 PM Samuel Holland
<samuel.holland at sifive.com> wrote:
>
> Instruction cache flush IPIs are sent only to CPUs in cpu_online_mask,
> so they will not target a CPU until it calls set_cpu_online() earlier in
> smp_callin(). As a result, if instruction memory is modified between the
> CPU coming out of reset and that point, then its instruction cache may
> contain stale data. Therefore, the instruction cache must be flushed
> after the set_cpu_online() synchronization point.
>
> Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
> Signed-off-by: Samuel Holland <samuel.holland at sifive.com>
> ---
>
> Changes in v4:
>  - New patch for v4
>
>  arch/riscv/kernel/smpboot.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index d162bf339beb..48af5bd3ec30 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -26,7 +26,7 @@
>  #include <linux/sched/task_stack.h>
>  #include <linux/sched/mm.h>
>
> -#include <asm/cpufeature.h>
> +#include <asm/cacheflush.h>
>  #include <asm/cpu_ops.h>
>  #include <asm/cpufeature.h>
>  #include <asm/irq.h>
> @@ -257,9 +257,10 @@ asmlinkage __visible void smp_callin(void)
>         riscv_user_isa_enable();
>
>         /*
> -        * Remote TLB flushes are ignored while the CPU is offline, so emit
> -        * a local TLB flush right now just in case.
> +        * Remote cache and TLB flushes are ignored while the CPU is offline,
> +        * so flush them both right now just in case.
>          */
> +       local_flush_icache_all();
>         local_flush_tlb_all();
>         complete(&cpu_running);
>         /*
> --
> 2.42.0
>

This looks good to me, so you can add:

Reviewed-by: Alexandre Ghiti <alexghiti at rivosinc.com>

Thanks,

Alex