[RFC PATCH 0/6] Add Pinctrl driver for Starfive JH8100 SoC

Yuklin Soo yuklin.soo at starfivetech.com
Thu Jan 4 00:28:10 PST 2024



> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Sent: Friday, December 22, 2023 12:20 AM
> To: Yuklin Soo <yuklin.soo at starfivetech.com>; Linus Walleij
> <linus.walleij at linaro.org>; Bartosz Golaszewski
> <bartosz.golaszewski at linaro.org>; Hal Feng <hal.feng at starfivetech.com>;
> Leyfoon Tan <leyfoon.tan at starfivetech.com>; Jianlong Huang
> <jianlong.huang at starfivetech.com>; Emil Renner Berthing
> <kernel at esmil.dk>; Rob Herring <robh at kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt at linaro.org>; Conor Dooley <conor+dt at kernel.org>;
> Drew Fustini <drew at beagleboard.org>
> Cc: linux-gpio at vger.kernel.org; linux-kernel at vger.kernel.org;
> devicetree at vger.kernel.org; linux-riscv at lists.infradead.org; Paul Walmsley
> <paul.walmsley at sifive.com>; Palmer Dabbelt <palmer at dabbelt.com>;
> Albert Ou <aou at eecs.berkeley.edu>
> Subject: Re: [RFC PATCH 0/6] Add Pinctrl driver for Starfive JH8100 SoC
> 
> On 21/12/2023 09:36, Alex Soo wrote:
> > Starfive JH8100 SoC consists of 4 pinctrl domains - sys_east,
> > sys_west, sys_gmac, and aon. This patch series adds pinctrl drivers
> > for these 4 pinctrl domains and this patch series is depending on the
> > JH8100 base patch series in [1] and [2].
> > The relevant dt-binding documentation for each pinctrl domain has been
> > updated accordingly.
> 
> Please explain why this is RFC. Every patch is RFC, so what is special about
> here? Usually this means work is not finished and should not be merged,
> neither reviewed. If you spelled out here the reasons, it would be easier for
> us to understand whether we should complain about broken and non-
> building code or not.

This JH8100 SoC pinctrl patch is dependent on the following: 
-	Initial device tree support and dt-bindings for JH8100 SoC
https://lore.kernel.org/lkml/20231214-platonic-unhearing-27e2ec3d8f75@spud/
-	Clock & Reset Support for JH8100 SoC
 https://lore.kernel.org/lkml/20231206115000.295825-1-jeeheng.sia@starfivetech.com/
 

Refer to the first link, there is maintainer feedback that if our evaluation platform is FPGA-based (since actual silicon is still unavailable), they are not keen on merging the patches, and things like pinctrl or clock drivers should first be submitted as “not to be merged”, in other words, as RFC patches.

> 
> Best regards,
> Krzysztof



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