[PATCH -fixes v4 0/3] riscv: cbo.zero fixes

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer at rivosinc.com>:

On Tue, 27 Feb 2024 22:55:32 -0800 you wrote:
> This series fixes a couple of issues related to using the cbo.zero
> instruction in userspace. The first patch fixes a bug where the wrong
> enable bit gets set if the kernel is running in M-mode. The remaining
> patches fix a bug where the enable bit gets reset to its default value
> after a nonretentive idle state. I have hardware which reproduces this:
> 
> Before this series:
>   $ tools/testing/selftests/riscv/hwprobe/cbo
>   TAP version 13
>   1..3
>   ok 1 Zicboz block size
>   # Zicboz block size: 64
>   Illegal instruction
> 
> [...]

Here is the summary with links:
  - [-fixes,v4,1/3] riscv: Fix enabling cbo.zero when running in M-mode
    https://git.kernel.org/riscv/c/3fb3f7164edc
  - [-fixes,v4,2/3] riscv: Add a custom ISA extension for the [ms]envcfg CSR
    https://git.kernel.org/riscv/c/4774848fef60
  - [-fixes,v4,3/3] riscv: Save/restore envcfg CSR during CPU suspend
    https://git.kernel.org/riscv/c/05ab803d1ad8

You are awesome, thank you!
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