[PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller

[Thomas Gleixner]

On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote:
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located. The base of custom interrupt number is set
> to 256.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as a private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node to
> enable the use of custom local interrupt source.
> e.g.,
>
>   cpu0: cpu at 0 {
>       compatible = "andestech,ax45mp", "riscv";
>       ...
>       cpu0-intc: interrupt-controller {
>           #interrupt-cells = <0x01>;
>           compatible = "andestech,cpu-intc", "riscv,cpu-intc";
>           interrupt-controller;
>       };
>   };
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Randolph <randolph at andestech.com>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Reviewed-by: Thomas Gleixner <tglx at linutronix.de>

Palmer, feel free to take this through the riscv tree. I have no other
changes pending against that driver.

Thanks,

        tglx