[PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property
Samuel Holland
samuel.holland at sifive.com
Sun Feb 18 07:29:11 PST 2024
Hi Krzysztof,
On 2024-02-17 3:00 AM, Krzysztof Kozlowski wrote:
> On 16/02/2024 01:08, Samuel Holland wrote:
>> The SiFive Composable Cache controller contains an optional PMU with a
>> configurable number of event counters. Document a property which
>
> Configurable in what context? By chip designers or by OS? Why this
> cannot be deduced from the compatible?
This parameter is configurable by the chip designers.
The information certainly can be deduced from the SoC-specific compatible
string, but doing so makes the driver only work on that specific list of SoCs.
When provided via a property, the driver can work without changes on any SoC
that uses this IP block. (None of the SoCs currently listed in the binding
contain a PMU, so there is no backward compatibility concern with adding the new
property.)
My understanding of the purpose of the SoC-specific compatible string is to
handle eventualities (silicon bugs, integration quirks, etc.), not to
intentionally limit the driver to a narrow list of hardware.
Regards,
Samuel
>> describes the number of available counters.
>>
>> Signed-off-by: Samuel Holland <samuel.holland at sifive.com>
>> ---
>>
>> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
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