[PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains
Claudiu
claudiu.beznea at tuxon.dev
Thu Feb 8 04:42:51 PST 2024
From: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
Instantiate always-on power domain for R9A07G043 SoC. At the moment, all
the IPs are part of this domain.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index acfb06cad441..3a7fddd1fa61 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -358,6 +358,11 @@ static const unsigned int r9a07g043_no_pm_mod_clks[] = {
};
#endif
+static const struct rzg2l_cpg_pm_domain_init_data r9a07g043_pm_domains[] = {
+ DEF_PD("always-on", R9A07G043_PD_ALWAYS_ON, 0, 0,
+ RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON),
+};
+
const struct rzg2l_cpg_info r9a07g043_cpg_info = {
/* Core Clocks */
.core_clks = r9a07g043_core_clks,
@@ -392,5 +397,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
#endif
+ /* Power domains. */
+ .pm_domains = r9a07g043_pm_domains,
+ .num_pm_domains = ARRAY_SIZE(r9a07g043_pm_domains),
+
.has_clk_mon_regs = true,
};
--
2.39.2
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