[PATCH v3 1/3] dt-bindings: riscv: add bfloat16 ISA extension description

[Jessica Clarke]

On 16 Dec 2024, at 22:00, Samuel Holland <samuel.holland at sifive.com> wrote:
> 
> On 2024-12-05 11:58 PM, Inochi Amaoto wrote:
>> Add description for the BFloat16 precision Floating-Point ISA extension,
>> (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62
>> ("Added Chapter title to BF16") of the riscv-isa-manual.
>> 
>> Signed-off-by: Inochi Amaoto <inochiama at gmail.com>
>> Acked-by: Conor Dooley <conor.dooley at microchip.com>
>> ---
>> .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++
>> 1 file changed, 45 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> index 9c7dd7e75e0c..0a1f1a76d129 100644
>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> @@ -329,6 +329,12 @@ properties:
>>             instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
>>             riscv-isa-manual.
>> 
>> +        - const: zfbfmin
>> +          description:
>> +            The standard Zfbfmin extension which provides minimal support for
>> +            16-bit half-precision brain floating-point instructions, as ratified
> 
> I think you mean "binary" here and in the entries below, not "brain”.

No, that’s Zfhmin / FP16 / binary16, not Zfbfmin / BF16 / BFloat16? The
B is for Brain as it came out of Google Brain.

https://en.wikipedia.org/wiki/Bfloat16_floating-point_format

Jess