[PATCH v2 1/1] RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation
patchwork-bot+linux-riscv at kernel.org
patchwork-bot+linux-riscv at kernel.org
Wed Dec 11 14:32:35 PST 2024
Hello:
This patch was applied to riscv/linux.git (fixes)
by Anup Patel <anup at brainfault.org>:
On Tue, 29 Oct 2024 16:55:39 +0800 you wrote:
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The pending bit is cleared whenever the rectified input value is
> low, when the interrupt is forwarded by MSI, or by a relevant
> write to an in_clrip register or to clripnum."
>
> [...]
Here is the summary with links:
- [v2,1/1] RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation
https://git.kernel.org/riscv/c/60821fb4dd73
You are awesome, thank you!
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