[PATCH v8 0/5] Add Svade and Svadu Extensions Support

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (fixes)
by Anup Patel <anup at brainfault.org>:

On Fri, 26 Jul 2024 16:49:25 +0800 you wrote:
> Svade and Svadu extensions represent two schemes for managing the PTE A/D
> bit. When the PTE A/D bits need to be set, Svade extension intdicates that
> a related page fault will be raised. In contrast, the Svadu extension
> supports hardware updating of PTE A/D bits. This series enables Svade and
> Svadu extensions for both host and guest OS.
> 
> Regrading the mailing thread[1], we have 4 possible combinations of
> these extensions in the device tree, the default hardware behavior for
> these possibilities are:
> 1) Neither Svade nor Svadu present in DT => It is technically
>    unknown whether the platform uses Svade or Svadu. Supervisor
>    software should be prepared to handle either hardware updating
>    of the PTE A/D bits or page faults when they need updated.
> 2) Only Svade present in DT => Supervisor must assume Svade to be
>    always enabled.
> 3) Only Svadu present in DT => Supervisor must assume Svadu to be
>    always enabled.
> 4) Both Svade and Svadu present in DT => Supervisor must assume
>    Svadu turned-off at boot time. To use Svadu, supervisor must
>    explicitly enable it using the SBI FWFT extension.
> 
> [...]

Here is the summary with links:
  - [v8,1/5] RISC-V: Add Svade and Svadu Extensions Support
    https://git.kernel.org/riscv/c/94a7734d0967
  - [v8,2/5] dt-bindings: riscv: Add Svade and Svadu Entries
    https://git.kernel.org/riscv/c/b8d481671703
  - [v8,3/5] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
    https://git.kernel.org/riscv/c/97eccf7db4f2
  - [v8,4/5] KVM: riscv: selftests: Fix compile error
    (no matching commit)
  - [v8,5/5] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test
    https://git.kernel.org/riscv/c/c74bfe4ffe8c

You are awesome, thank you!
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