[PATCH 1/4] irqchip/riscv-imsic: Handle non-atomic MSI updates for device
Anup Patel
apatel at ventanamicro.com
Mon Dec 9 04:08:18 PST 2024
Hi Thomas,
On Mon, Dec 9, 2024 at 1:44 AM Thomas Gleixner <tglx at linutronix.de> wrote:
>
> On Sun, Dec 08 2024 at 20:37, Anup Patel wrote:
> > +
> > + tvec = vec->local_id == mvec->local_id ?
> > + NULL : &lpriv->vectors[mvec->local_id];
> > + if (tvec && __imsic_id_read_clear_pending(tvec->local_id)) {
>
> As I told you before:
>
> I don't see a way how that can work remote with the IMSIC either even if
> you can easily access the pending state of the remote CPU:
For RISC-V IMSIC, a remote CPU cannot access the pending state
of interrupts on some other CPU.
>
> CPU0 CPU1 Device
> set_affinity()
> write_msg(tmp)
> write(addr); // CPU1
> write(data); // vector 0x20
> raise IRQ (CPU1, vector 0x20)
> handle vector 0x20
> (other device)
>
> check_pending(CPU1, 0x20) == false -> Interrupt is lost
>
> There is no guarantee that set_affinity() runs on the original target
> CPU (CPU 1). Your scheme only works, when CPU1 vector 0x20 is not used
> by some other device. If it's used, you lost as CPU1 will consume the
> vector and your pending check is not seeing anything.
>
> x86 ensures CPU locality by deferring the affinity move to the next
> device interrupt on the original target CPU (CPU1 in the above
> example). See CONFIG_GENERIC_IRQ_PENDING.
I agree with you.
The IMSIC driver must do the affinity move upon the next device
interrupt on the old CPU. I will update this patch in the next revision.
BTW, I did not find CONFIG_GENERIC_IRQ_PENDING. Is the
name correct ?
>
> The interrupt domains which are not affected (remap) set the
> IRQ_MOVE_PCNTXT flag to avoid that dance and don't use that affinity
> setter code path at all.
Yes, setting the IRQ_MOVE_PCNTXT flag in the remap domain
makes perfect sense.
I suggest adding IRQ_MOVE_PCNTXT usage as part of Drew's
irqbypass series which adds a remap domain in the IOMMU
driver. Unless you insist on having it as part of this series ?
Regards,
Anup
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