[RFC PATCH v1 05/14] dt-bindings: clock: thead,th1520: Add support for Video Output subsystem
Stephen Boyd
sboyd at kernel.org
Wed Dec 4 12:21:11 PST 2024
Quoting Michal Wilczynski (2024-12-04 02:11:26)
> On 12/3/24 16:45, Krzysztof Kozlowski wrote:
> > On 03/12/2024 14:41, Michal Wilczynski wrote:
>
> [1] - https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20Video%20Image%20Processing%20User%20Manual.pdf
> >
> >> + these registers reside in the same address space, access to
> >> + them is coordinated through a shared syscon regmap provided by
> >> + the specified syscon node.
> >
> > Drop last sentence. syscon regmap is a Linux term, not hardware one.
> >
> > Anyway, this needs to be constrained per variant.
> >
> >> +
> >> "#clock-cells":
> >> const: 1
> >> description:
> >> @@ -36,8 +51,6 @@ properties:
> >>
> >> required:
> >> - compatible
> >> - - reg
> >
> > No, that's a clear NAK. You claim you have no address space but in the
> > same time you have address space via regmap.
>
> I see your concern. The VOSYS subsystem's address space includes
> registers for various components, such as clock gates and reset
> controls, which are scattered throughout the address space as specified
> in the manual 4.4.1 [2]. Initially, I attempted to use a shared syscon
> regmap for access, but I realize this might not be the best approach.
>
> To address this, I'll specify the 'reg' property in each node to define
> the address ranges explicitly fragmenting the address space for the VOSYS
> manually.
>
> vosys_clk: clock-controller at ffef528050 {
> compatible = "thead,th1520-clk-vo";
> reg = <0xff 0xef528050 0x0 0x8>;
> #clock-cells = <1>;
> };
>
> pd: power-domain at ffef528000 {
> compatible = "thead,th1520-pd";
> reg = <0xff 0xef528000 0x0 0x8>;
> #power-domain-cells = <1>;
> };
You should have one node:
clock-controller at ffef528000 {
compatible = "thead,th1520-vo";
reg = <0xff 0xef528050 0x0 0x1a04>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
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