[PATCH 1/3] dt-bindings: reset: sifive: add fu540/fu740 reset indexes

[Bo Gan]

Add bindings for FU540/FU740 clock/reset controller. The header is taken
from the same path in U-Boot with macros renamed to have FU540/740 prefix.

Signed-off-by: Bo Gan <ganboing at gmail.com>
---
 include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++
 include/dt-bindings/reset/sifive-fu740-prci.h | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h
 create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h

diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h
new file mode 100644
index 000000000000..dbaf602262d2
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu540-prci.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Sifive, Inc.
+ * Author: Sagar Kadam <sagar.kadam at sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define FU540_PRCI_RST_DDR_CTRL_N	0
+#define FU540_PRCI_RST_DDR_AXI_N	1
+#define FU540_PRCI_RST_DDR_AHB_N	2
+#define FU540_PRCI_RST_DDR_PHY_N	3
+/* bit 4 is reserved bit */
+#define FU540_PRCI_RST_RSVD_N		4
+#define FU540_PRCI_RST_GEMGXL_N		5
+
+#endif
diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h
new file mode 100644
index 000000000000..74d60ca9f1df
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu740-prci.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2020-2021 Sifive, Inc.
+ * Author: Pragnesh Patel <pragnesh.patel at sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define FU740_PRCI_RST_DDR_CTRL_N	0
+#define FU740_PRCI_RST_DDR_AXI_N	1
+#define FU740_PRCI_RST_DDR_AHB_N	2
+#define FU740_PRCI_RST_DDR_PHY_N	3
+#define FU740_PRCI_RST_PCIE_POWER_UP_N	4
+#define FU740_PRCI_RST_GEMGXL_N		5
+#define FU740_PRCI_RST_CLTX_N		6
+
+#endif
-- 
2.34.1