[PATCH -fixes v2] riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array

[Alexandre Ghiti]

On Thu, Aug 15, 2024 at 12:26 AM Conor Dooley <conor at kernel.org> wrote:
>
> On Wed, Aug 14, 2024 at 09:26:19PM +0200, Alexandre Ghiti wrote:
> > The out-of-bounds access is reported by UBSAN:
> >
> > [    0.000000] UBSAN: array-index-out-of-bounds in ../arch/riscv/kernel/vendor_extensions.c:41:66
> > [    0.000000] index -1 is out of range for type 'riscv_isavendorinfo [32]'
> > [    0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 6.11.0-rc2ubuntu-defconfig #2
> > [    0.000000] Hardware name: riscv-virtio,qemu (DT)
> > [    0.000000] Call Trace:
> > [    0.000000] [<ffffffff94e078ba>] dump_backtrace+0x32/0x40
> > [    0.000000] [<ffffffff95c83c1a>] show_stack+0x38/0x44
> > [    0.000000] [<ffffffff95c94614>] dump_stack_lvl+0x70/0x9c
> > [    0.000000] [<ffffffff95c94658>] dump_stack+0x18/0x20
> > [    0.000000] [<ffffffff95c8bbb2>] ubsan_epilogue+0x10/0x46
> > [    0.000000] [<ffffffff95485a82>] __ubsan_handle_out_of_bounds+0x94/0x9c
> > [    0.000000] [<ffffffff94e09442>] __riscv_isa_vendor_extension_available+0x90/0x92
> > [    0.000000] [<ffffffff94e043b6>] riscv_cpufeature_patch_func+0xc4/0x148
> > [    0.000000] [<ffffffff94e035f8>] _apply_alternatives+0x42/0x50
> > [    0.000000] [<ffffffff95e04196>] apply_boot_alternatives+0x3c/0x100
> > [    0.000000] [<ffffffff95e05b52>] setup_arch+0x85a/0x8bc
> > [    0.000000] [<ffffffff95e00ca0>] start_kernel+0xa4/0xfb6
> >
> > The dereferencing using cpu should actually not happen, so remove it.
> >
> > Fixes: 23c996fc2bc1 ("riscv: Extend cpufeature.c to detect vendor extensions")
> > Signed-off-by: Alexandre Ghiti <alexghiti at rivosinc.com>
> > ---
>
> You're missing a changelog here, which is doubly important when you drop
> tags provided to you on an earlier version.

Yes, you're right.

>
> >  arch/riscv/kernel/vendor_extensions.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
> > index b6c1e7b5d34b..a8126d118341 100644
> > --- a/arch/riscv/kernel/vendor_extensions.c
> > +++ b/arch/riscv/kernel/vendor_extensions.c
> > @@ -38,7 +38,7 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
> >       #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
> >       case ANDES_VENDOR_ID:
> >               bmap = &riscv_isa_vendor_ext_list_andes.all_harts_isa_bitmap;
> > -             cpu_bmap = &riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap[cpu];
> > +             cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
> >               break;
> >       #endif
> >       default:
> > --
> > 2.39.2
> >
> >