[PATCH v8 7/7] iommu/riscv: Paging domain support

[Easwar Hariharan]

On 6/14/2024 10:27 PM, Tomasz Jeznach wrote:
> Introduce first-stage address translation support.
> 
> Page table configured by the IOMMU driver will use the highest mode
> implemented by the hardware, unless not known at the domain allocation
> time falling back to the CPU’s MMU page mode.
> 
> This change introduces IOTINVAL.VMA command, required to invalidate
> any cached IOATC entries after mapping is updated and/or removed from
> the paging domain.  Invalidations for the non-leaf page entries use
> IOTINVAL for all addresses assigned to the protection domain for
> hardware not supporting more granular non-leaf page table cache
> invalidations.
> 
> Reviewed-by: Lu Baolu <baolu.lu at linux.intel.com>
> Reviewed-by: Zong Li <zong.li at sifive.com>
> Signed-off-by: Tomasz Jeznach <tjeznach at rivosinc.com>
> ---
>  drivers/iommu/riscv/iommu.c | 642 +++++++++++++++++++++++++++++++++++-
>  1 file changed, 639 insertions(+), 3 deletions(-)
> 

> @@ -856,7 +1473,7 @@ static struct iommu_domain riscv_iommu_identity_domain = {
>  
>  static int riscv_iommu_device_domain_type(struct device *dev)
>  {
> -	return IOMMU_DOMAIN_IDENTITY;
> +	return 0;
>  }

<snip>
Sorry for the drive by comment, I just happen to be in the nearby code
context.

Nit: It may be better to use IOMMU_DOMAIN_BLOCKED here for readability
rather than the bare value.

Thanks,
Easwar