[PATCH 2/4] riscv: boot: dts: thead: Fix node ordering in TH1520 device tree
Thomas Bonnefille
thomas.bonnefille at bootlin.com
Thu Apr 25 01:21:33 PDT 2024
According to the device tree coding style, nodes shall be ordered by
unit address in ascending order.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille at bootlin.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 54 +++++++++++++--------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 8b915e206f3a..d2fa25839012 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -193,6 +193,33 @@ uart0: serial at ffe7014000 {
status = "disabled";
};
+ emmc: mmc at ffe7080000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
+ sdio0: mmc at ffe7090000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
+ sdio1: mmc at ffe70a0000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe70a0000 0x0 0x10000>;
+ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
uart1: serial at ffe7f00000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f00000 0x0 0x100>;
@@ -311,33 +338,6 @@ dmac0: dma-controller at ffefc00000 {
status = "disabled";
};
- emmc: mmc at ffe7080000 {
- compatible = "thead,th1520-dwcmshc";
- reg = <0xff 0xe7080000 0x0 0x10000>;
- interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
- clock-names = "core";
- status = "disabled";
- };
-
- sdio0: mmc at ffe7090000 {
- compatible = "thead,th1520-dwcmshc";
- reg = <0xff 0xe7090000 0x0 0x10000>;
- interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
- clock-names = "core";
- status = "disabled";
- };
-
- sdio1: mmc at ffe70a0000 {
- compatible = "thead,th1520-dwcmshc";
- reg = <0xff 0xe70a0000 0x0 0x10000>;
- interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
- clock-names = "core";
- status = "disabled";
- };
-
timer0: timer at ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;
--
2.44.0
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