[PATCH v6 01/13] riscv: Flush the instruction cache during SMP bringup

[Alexandre Ghiti]

Hi Samuel,

On 27/03/2024 05:49, Samuel Holland wrote:
> Instruction cache flush IPIs are sent only to CPUs in cpu_online_mask,
> so they will not target a CPU until it calls set_cpu_online() earlier in
> smp_callin(). As a result, if instruction memory is modified between the
> CPU coming out of reset and that point, then its instruction cache may
> contain stale data. Therefore, the instruction cache must be flushed
> after the set_cpu_online() synchronization point.
>
> Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
> Reviewed-by: Alexandre Ghiti <alexghiti at rivosinc.com>
> Signed-off-by: Samuel Holland <samuel.holland at sifive.com>
> ---
>
> (no changes since v4)
>
> Changes in v4:
>   - New patch for v4
>
>   arch/riscv/kernel/smpboot.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index d41090fc3203..4b3c50da48ba 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -26,7 +26,7 @@
>   #include <linux/sched/task_stack.h>
>   #include <linux/sched/mm.h>
>   
> -#include <asm/cpufeature.h>
> +#include <asm/cacheflush.h>
>   #include <asm/cpu_ops.h>
>   #include <asm/irq.h>
>   #include <asm/mmu_context.h>
> @@ -234,9 +234,10 @@ asmlinkage __visible void smp_callin(void)
>   	riscv_user_isa_enable();
>   
>   	/*
> -	 * Remote TLB flushes are ignored while the CPU is offline, so emit
> -	 * a local TLB flush right now just in case.
> +	 * Remote cache and TLB flushes are ignored while the CPU is offline,
> +	 * so flush them both right now just in case.
>   	 */
> +	local_flush_icache_all();
>   	local_flush_tlb_all();
>   	complete(&cpu_running);
>   	/*


This should go into -fixes, would you mind sending this patch on its 
own? I think it is easier for Palmer.

Thanks,

Alex