[PATCH v3 07/11] dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi

[Chen Wang]

From: Inochi Amaoto <inochiama at outlook.com>

Like the timer of Sophgo sg2042 clint. The machine-level software
interrupt device (mswi) of sg2042 clint have the same problem when
dealing with the standard sifive clint.

To avoid the same conficts as the timer of sg2042 clint, also add the
vendor specific compatible string to identify the mswi of sg2042 clint.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Signed-off-by: Chen Wang <wangchen20 at iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw at gmail.com>
---
 .../sophgo,sg2042-clint-mswi.yaml             | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
new file mode 100644
index 000000000000..a79c4c3db3b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-clint-mswi.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-clint-mswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
+
+maintainers:
+  - Inochi Amaoto <inochiama at outlook.com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: sophgo,sg2042-clint-mswi
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller at 94000000 {
+      compatible = "sophgo,sg2042-clint-mswi";
+      interrupts-extended = <&cpu1intc 3>,
+                            <&cpu2intc 3>,
+                            <&cpu3intc 3>,
+                            <&cpu4intc 3>;
+      reg = <0x94000000 0x00010000>;
+    };
+...
-- 
2.25.1