[PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles

[Chen Wang]

The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO's SG2042 SoC.

Acked-by: Chao Wei <chao.wei at sophgo.com>
Reviewed-by: Guo Ren <guoren at kernel.org>
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
Signed-off-by: Chen Wang <wangchen20 at iscas.ac.cn>
Signed-off-by: Chen Wang <unicornxw at gmail.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 38c0b5213736..185a0191bad6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -47,6 +47,7 @@ properties:
               - sifive,u74-mc
               - thead,c906
               - thead,c910
+              - thead,c920
           - const: riscv
       - items:
           - enum:
-- 
2.25.1