[RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

[Icenowy Zheng]

在 2023-09-22星期五的 09:13 +0100，Conor Dooley写道：
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> Convert the th1520 devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi
> b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ce708183b6f6..723f65487246 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -20,6 +20,9 @@ c910_0: cpu at 0 {
>                         compatible = "thead,c910", "riscv";
>                         device_type = "cpu";
>                         riscv,isa = "rv64imafdc";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "zicntr", "zicsr",
> +                                              "zifencei", "zihpm";

Zfh is supported by T-Head C9xx with float too.

In addition, should X extensions get listed here?

>                         reg = <0>;
>                         i-cache-block-size = <64>;
>                         i-cache-size = <65536>;
> @@ -41,6 +44,9 @@ c910_1: cpu at 1 {
>                         compatible = "thead,c910", "riscv";
>                         device_type = "cpu";
>                         riscv,isa = "rv64imafdc";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "zicntr", "zicsr",
> +                                              "zifencei", "zihpm";
>                         reg = <1>;
>                         i-cache-block-size = <64>;
>                         i-cache-size = <65536>;
> @@ -62,6 +68,9 @@ c910_2: cpu at 2 {
>                         compatible = "thead,c910", "riscv";
>                         device_type = "cpu";
>                         riscv,isa = "rv64imafdc";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "zicntr", "zicsr",
> +                                              "zifencei", "zihpm";
>                         reg = <2>;
>                         i-cache-block-size = <64>;
>                         i-cache-size = <65536>;
> @@ -83,6 +92,9 @@ c910_3: cpu at 3 {
>                         compatible = "thead,c910", "riscv";
>                         device_type = "cpu";
>                         riscv,isa = "rv64imafdc";
> +                       riscv,isa-base = "rv64i";
> +                       riscv,isa-extensions = "i", "m", "a", "f",
> "d", "c", "zicntr", "zicsr",
> +                                              "zifencei", "zihpm";
>                         reg = <3>;
>                         i-cache-block-size = <64>;
>                         i-cache-size = <65536>;