[PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint

[Inochi Amaoto]

>
>On Fri, Sep 22, 2023 at 01:16:35PM +0800, Inochi Amaoto wrote:
>
>>>> The SiFive CLINT has flexibility related limitations which makes it
>>>> not useful for multi-socket and mult-die systems. The SiFive CLINT
>>>> is also not useful for systems with AIA because with AIA M-mode has
>>>> a new way of doing M-mode IPIs. Due to this reasons, the RISC-V
>>>> ACLINT spec breaks down traditional SiFive CLINT into two separate
>>>> devices namely mtimer and mswi. This allows platforms to implement
>>>> only the required set of devices. The mtimer as defined by the ACLINT
>>>> specifications also allows platforms to place mtime and mtimecmp
>>>> registers at different locations.
>>>>
>>>> Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>>>>
>>>> We need a separate DT bindings document for ACLINT MTIMER
>>>> and ACLINT MSWI because these are separate devices. The
>>>> Sophgo sg2042 SoC should add their implementation specific
>>>> compatible strings in this document.
>>>
>>> If the spec isn't frozen, I'm not accepting a binding for the "generic"
>>> version of it. Bindings for this specific implemtnation are okay.
>>> For sure though, squeezing this into the sifive,plic binding isn't
>>> appropriate.
>>>
>>
>> It seems I have missed a point. I wonder whether it is better to add a
>> "aclint" binding firstly and then add sg2042 to it, or just use sg2042
>> specific binding?
>
>sg2042 specific, being frozen is a requirement for merging patches
>related to RVI specifications.
>

Thanks

>> If use "aclint" binding, I wonder it is OK to add
>> thead quirks as compatible specific properties, or left this to the SBI to
>> handle? e.g. T-HEAD timer is not 64bit timer, and we should identify this.
>
>The compatible string alone should be sufficient to identify the width
>of the timer etc.
>

OK, I will take it

>Thanks,
>Conor.
>