[RFC PATCH 6/6] riscv: Add BLAKE2s V implementation

[Björn Töpel]

Conor Dooley <conor.dooley at microchip.com> writes:

> On Tue, Sep 12, 2023 at 01:57:28PM +0200, Björn Töpel wrote:
>> From: Björn Töpel <bjorn at rivosinc.com>
>> 
>> BLAKE2s is used in various places, most notably in Wireguard, and as
>> of v5.17 in drivers/char/random.
>> 
>> Add a BLAKE2s implementation using the V-extension. This is a
>> translation of the x86-64 AVX512 variant
>> (arch/x86/crypto/blake2s-core.S) to the RISC-V V-extension.
>> 
>> The AVX512 variant requires registers >= 256b (ymm*), and hence this
>> implementation requires a VLEN of >=256.
>> 
>> The implementation passes the kernel BLAKE2s selftest, and has been
>> tested on spike and qemu.
>> 
>> Instruction-wise, the V-variant uses 60% less instructions than the
>> generic, C-based, implementation.
>> 
>> Signed-off-by: Björn Töpel <bjorn at rivosinc.com>
>
>>  arch/riscv/crypto/blake2s-v.S    | 164 +++++++++++++++++++++++++++++++
>
>
> This file is currently being built for !RISCV_ISA_V, leading to build errors
> for obvious reasons. Eg:
> ../arch/riscv/crypto/blake2s-v.S:62:2: error: instruction requires the
> following: 'V' (Vector Extension for Application Processors), 'Zve32x'
> or 'Zve64x' (Vector Extensions for Embedded Processors)

Thanks, noted for the next rev!