[PATCH bpf-next 4/6] riscv, bpf: Add necessary Zbb instructions

[Conor Dooley]

On Wed, Sep 13, 2023 at 11:34:11PM +0800, Pu Lehui wrote:
> From: Pu Lehui <pulehui at huawei.com>
> 
> Add necessary Zbb instructions introduced by [0] to reduce code size and
> improve performance of RV64 JIT. At the same time, a helper is added to
> check whether the CPU supports Zbb instructions.
> 
> [0] https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf
> 
> Signed-off-by: Pu Lehui <pulehui at huawei.com>
> ---
>  arch/riscv/net/bpf_jit.h | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> index 8e0ef4d08..7ee59d1f6 100644
> --- a/arch/riscv/net/bpf_jit.h
> +++ b/arch/riscv/net/bpf_jit.h
> @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
>  	return IS_ENABLED(CONFIG_RISCV_ISA_C);
>  }
>  
> +static inline bool rvzbb_enabled(void)
> +{
> +	return IS_ENABLED(CONFIG_RISCV_ISA_ZBB);
> +}

I dunno much about bpf, so passing question that may be a bit obvious:
Is this meant to be a test as to whether the kernel binary is built with
support for the extension, or whether the underlying platform is capable
of executing zbb instructions.

Sorry if that would be obvious to a bpf aficionado, context I have here
is the later user and the above rvc_enabled() test, which functions
differently to Zbb and so doesn't really help me.

Thanks,
Conor.

> +
>  enum {
>  	RV_REG_ZERO =	0,	/* The constant value 0 */
>  	RV_REG_RA =	1,	/* Return address */
> @@ -727,6 +732,27 @@ static inline u16 rvc_swsp(u32 imm8, u8 rs2)
>  	return rv_css_insn(0x6, imm, rs2, 0x2);
>  }
>  
> +/* RVZBB instrutions. */
> +static inline u32 rvzbb_sextb(u8 rd, u8 rs1)
> +{
> +       return rv_i_insn(0x604, rs1, 1, rd, 0x13);
> +}
> +
> +static inline u32 rvzbb_sexth(u8 rd, u8 rs1)
> +{
> +       return rv_i_insn(0x605, rs1, 1, rd, 0x13);
> +}
> +
> +static inline u32 rvzbb_zexth(u8 rd, u8 rs)
> +{
> +       return rv_i_insn(0x80, rs, 4, rd, __riscv_xlen == 64 ? 0x3b : 0x33);
> +}
> +
> +static inline u32 rvzbb_rev8(u8 rd, u8 rs)
> +{
> +       return rv_i_insn(__riscv_xlen == 64 ? 0x6b8 : 0x698, rs, 5, rd, 0x13);
> +}
> +
>  /*
>   * RV64-only instructions.
>   *
> -- 
> 2.25.1
> 
> 
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