[PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus

[Conor Dooley]

On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote:
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
> 
> Signed-off-by: Jisheng Zhang <jszhang at kernel.org>
> Tested-by: Drew Fustini <dfustini at baylibre.com>
> ---
> 
> Since v1:
>  - rebase on v6.6-rc1
>  - collect Tested-by tag

Does this mean you're expecting me to take this?

> 
>  arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ce708183b6f6..ff364709a6df 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -139,6 +139,7 @@ soc {
>  		interrupt-parent = <&plic>;
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> +		dma-noncoherent;
>  		ranges;
>  
>  		plic: interrupt-controller at ffd8000000 {
> -- 
> 2.40.1
> 
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