[RFC PATCH 0/6] RISC-V BLAKE2s Vector implementation
Björn Töpel
bjorn at kernel.org
Tue Sep 12 04:57:22 PDT 2023
From: Björn Töpel <bjorn at rivosinc.com>
Hi,
This is Andy's kernel mode vector V2 series [1], with my BLAKE2s
AVX-512-to-RISC-V translation patch appended.
I've tagged it as RFC, since Andy's series is still not in-tree yet.
It's a first step towards a Vector aided Wireguard! ;-)
Cheers,
Björn
[1] https://lore.kernel.org/linux-riscv/20230721112855.1006-1-andy.chiu@sifive.com/
Andy Chiu (3):
riscv: sched: defer restoring Vector context for user
riscv: vector: do not pass task_struct into
riscv_v_vstate_{save,restore}()
riscv: vector: allow kernel-mode Vector with preemption
Björn Töpel (1):
riscv: Add BLAKE2s V implementation
Greentime Hu (2):
riscv: Add support for kernel mode vector
riscv: Add vector extension XOR implementation
arch/riscv/Kbuild | 2 +-
arch/riscv/Kconfig | 10 ++
arch/riscv/crypto/Kconfig | 16 +++
arch/riscv/crypto/Makefile | 6 +
arch/riscv/crypto/blake2s-glue.c | 39 ++++++
arch/riscv/crypto/blake2s-v.S | 164 +++++++++++++++++++++++++
arch/riscv/include/asm/entry-common.h | 13 ++
arch/riscv/include/asm/processor.h | 2 +
arch/riscv/include/asm/simd.h | 52 ++++++++
arch/riscv/include/asm/thread_info.h | 6 +
arch/riscv/include/asm/vector.h | 50 ++++++--
arch/riscv/include/asm/xor.h | 82 +++++++++++++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/asm-offsets.c | 2 +
arch/riscv/kernel/entry.S | 45 +++++++
arch/riscv/kernel/kernel_mode_vector.c | 146 ++++++++++++++++++++++
arch/riscv/kernel/process.c | 10 +-
arch/riscv/kernel/ptrace.c | 2 +-
arch/riscv/kernel/signal.c | 4 +-
arch/riscv/kernel/vector.c | 5 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/xor.S | 81 ++++++++++++
crypto/Kconfig | 3 +
drivers/net/Kconfig | 1 +
24 files changed, 725 insertions(+), 18 deletions(-)
create mode 100644 arch/riscv/crypto/Kconfig
create mode 100644 arch/riscv/crypto/Makefile
create mode 100644 arch/riscv/crypto/blake2s-glue.c
create mode 100644 arch/riscv/crypto/blake2s-v.S
create mode 100644 arch/riscv/include/asm/simd.h
create mode 100644 arch/riscv/include/asm/xor.h
create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
create mode 100644 arch/riscv/lib/xor.S
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
--
2.39.2
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