[PATCH v4] riscv: dts: allwinner: d1: Add PMU event node

[Jernej Škrabec]

On Monday, August 28, 2023 6:30:22 AM CEST Inochi Amaoto wrote:
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
> Link:
> https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/
> pmu/rtl/aq_hpcp_top.v#L657 

Acked-by: Jernej Skrabec <jernej.skrabec at gmail.com>

What's the status of dependencies? Are they merged?

Best regards,
Jernej

> ---
> changed from v3:
> 1. remove wrong event mapping of 0x0000a
> 2. add reference url of c906 events implementation (D1 only support events
> described in R1S0 user manual, but event mapping is the same)
> 
> changed from v2:
> 1. move pmu node from /soc to / to avoid warnings when checking.
> 
> The meaning of T-HEAD events can be found in this pending patch:
> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BB
> E2A at IA1PR20MB4953.namprd20.prod.outlook.com
> 
> The patch above also provides a example that shows how to setup
> environment and use perf with T-HEAD events.
> ---
>  arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index
> 8275630af977..53a984d78e3f 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -73,4 +73,43 @@ plic: interrupt-controller at 10000000 {
>  			#interrupt-cells = <2>;
>  		};
>  	};
> +
> +	pmu {
> +		compatible = "riscv,pmu";
> +		riscv,event-to-mhpmcounters =
> +			<0x00003 0x00003 0x00000008>,
> +			<0x00004 0x00004 0x00000010>,
> +			<0x00005 0x00005 0x00000200>,
> +			<0x00006 0x00006 0x00000100>,
> +			<0x10000 0x10000 0x00004000>,
> +			<0x10001 0x10001 0x00008000>,
> +			<0x10002 0x10002 0x00010000>,
> +			<0x10003 0x10003 0x00020000>,
> +			<0x10019 0x10019 0x00000040>,
> +			<0x10021 0x10021 0x00000020>;
> +		riscv,event-to-mhpmevent =
> +			<0x00003 0x00000000 0x00000001>,
> +			<0x00004 0x00000000 0x00000002>,
> +			<0x00005 0x00000000 0x00000007>,
> +			<0x00006 0x00000000 0x00000006>,
> +			<0x10000 0x00000000 0x0000000c>,
> +			<0x10001 0x00000000 0x0000000d>,
> +			<0x10002 0x00000000 0x0000000e>,
> +			<0x10003 0x00000000 0x0000000f>,
> +			<0x10019 0x00000000 0x00000004>,
> +			<0x10021 0x00000000 0x00000003>;
> +		riscv,raw-event-to-mhpmcounters =
> +			<0x00000000 0x00000001 0xffffffff 0xffffffff 
0x00000008>,
> +			<0x00000000 0x00000002 0xffffffff 0xffffffff 
0x00000010>,
> +			<0x00000000 0x00000003 0xffffffff 0xffffffff 
0x00000020>,
> +			<0x00000000 0x00000004 0xffffffff 0xffffffff 
0x00000040>,
> +			<0x00000000 0x00000005 0xffffffff 0xffffffff 
0x00000080>,
> +			<0x00000000 0x00000006 0xffffffff 0xffffffff 
0x00000100>,
> +			<0x00000000 0x00000007 0xffffffff 0xffffffff 
0x00000200>,
> +			<0x00000000 0x0000000b 0xffffffff 0xffffffff 
0x00002000>,
> +			<0x00000000 0x0000000c 0xffffffff 0xffffffff 
0x00004000>,
> +			<0x00000000 0x0000000d 0xffffffff 0xffffffff 
0x00008000>,
> +			<0x00000000 0x0000000e 0xffffffff 0xffffffff 
0x00010000>,
> +			<0x00000000 0x0000000f 0xffffffff 0xffffffff 
0x00020000>;
> +	};
>  };
> --
> 2.42.0