[PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding

[Drew Fustini]

On Sun, Aug 27, 2023 at 05:08:12PM +0800, Jisheng Zhang wrote:
> From: Icenowy Zheng <uwu at icenowy.me>
> 
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
> 
> Fix this in the comment and in the hardcoded instruction.
> 
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> Reviewed-by: Heiko Stuebner <heiko at sntech.de>
> Reviewed-by: Guo Ren <guoren at kernel.org>
> ---
>  arch/riscv/include/asm/errata_list.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index fb1a810f3d8c..feab334dd832 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE(						\
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
>   *   0000001    01001      rs1       000      00000  0001011
>   * dcache.cva rs1 (clean, virtual address)
> - *   0000001    00100      rs1       000      00000  0001011
> + *   0000001    00101      rs1       000      00000  0001011
>   *
>   * dcache.cipa rs1 (clean then invalidate, physical address)
>   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE(						\
>   *   0000000    11001     00000      000      00000  0001011
>   */
>  #define THEAD_inval_A0	".long 0x0265000b"
> -#define THEAD_clean_A0	".long 0x0245000b"
> +#define THEAD_clean_A0	".long 0x0255000b"
>  #define THEAD_flush_A0	".long 0x0275000b"
>  #define THEAD_SYNC_S	".long 0x0190000b"
>  
> -- 
> 2.40.1
> 

Tested-by: Drew Fustini <dfustini at baylibre.com>

I applied this on top of the emmc series [1] and the dma-noncoherent dts
patch [2]. SDMA is now working with this patch applied. Before this
patch, the filesystems on the emmc were corrupted after mounting. It
makes sense that problem is solved by the correct cache clean
instruction being used.

Thanks,
Drew

[1] https://lore.kernel.org/linux-riscv/20230724-th1520-emmc-v2-0-132ed2e2171e@baylibre.com/
[2] https://lore.kernel.org/linux-riscv/ZOIBQI3L4kP7c%2FT1@xhacker/