[PATCH v2 1/2] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
Emil Renner Berthing
emil.renner.berthing at canonical.com
Tue Oct 31 07:14:43 PDT 2023
This cache controller is also used on the StarFive JH7100 SoC.
Unfortunately it needs a quirk to work properly, so add dedicated
compatible string to be able to match it.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing at canonical.com>
---
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 8a6a78e1a7ab..7e8cebe21584 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -38,7 +38,9 @@ properties:
- sifive,fu740-c000-ccache
- const: cache
- items:
- - const: starfive,jh7110-ccache
+ - enum:
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
@@ -88,6 +90,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -111,6 +114,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
--
2.40.1
More information about the linux-riscv
mailing list