[PATCH] dt-bindings: riscv: Document cbop-block-size

[Daniel Henrique Barboza]

On 10/29/23 11:53, Conor Dooley wrote:
> Yo,
> 
> On Sun, Oct 29, 2023 at 09:35:00AM -0300, Daniel Henrique Barboza wrote:
>> Following the examples of cbom-block-size and cboz-block-size,
>> cbop-block-size is the cache size of Zicbop (cbo.prefetch) operations.
>> The most common case is to have all cache block sizes to be the same
>> size (e.g. profiles such as rva22u64 mandates a 64 bytes size for all
>> cache operations), but there's no specification requirement for that,
>> and an implementation can have different cache sizes for each operation.
>>
>> Cc: Rob Herring <robh at kernel.org>
>> Cc: Conor Dooley <conor.dooley at microchip.com>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza at ventanamicro.com>
> 
> Firstly, odd CC list. Please CC the output of get_maintainer.pl in the
> future.

Ops, my bad

> 
> IIRC, I mentioned defining this to Drew when he was add zicboz, but he
> didn't want to add it - although he seems to have asked you to document
> this. Drew, change of heart or am I not remembering correctly?
> I think he cited some interpretation of the spec from Andrei W that
> implied the Zicbop size would be the same as one of the other ones, but
> I cannot find that on lore atm.

The reason why I'm here is because I want to add Zicbop in QEMU riscv,isa.
I'm pushing a rva22u64 profile implementation there and Zicbop is mandatory
for it. In the process I added a riscv,cbop-block-size DT because, well,
if both Zicboz and Zicbom have their respective block-size DTs, then it's
expected that Zicbop also has one. Or so I thought.

Drew then replied in the QEMU ML [1] that riscv,cbop-block-size isn't
documented and we can't add it as it is. So here we are.

If riscv,cbop-block-size isn't needed because Zicbop will use the cache
block size of Zicboz or Zicbom, that works for me too - I'll add a note
in QEMU explaining why there's no riscv,cbop-block-size and everything
is fine. What we can't do is add stuff in the QEMU DT that's neither
documented nor acked in the DT bindings.


Thanks,


Daniel

[1] https://lore.kernel.org/qemu-riscv/20231028-2d6bf00dddc7bc4a25b32663@orel/

> 
> If Drew's okay with it, then I am too, so a conditional
> Acked-by: Conor Dooley <conor.dooley at microchip.com>
> 
> Cheers,
> Conor.
> 
>> ---
>>   Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> index 97e8441eda1c..1660b296f7de 100644
>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> @@ -78,6 +78,11 @@ properties:
>>       description:
>>         The blocksize in bytes for the Zicbom cache operations.
>>   
>> +  riscv,cbop-block-size:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    description:
>> +      The blocksize in bytes for the Zicbop cache operations.
>> +
>>     riscv,cboz-block-size:
>>       $ref: /schemas/types.yaml#/definitions/uint32
>>       description:
>> -- 
>> 2.41.0
>>
>>