[PATCH v1] riscv: dts: sophgo: remove address-cells from intc node

[Chen Wang]

On 2023/10/24 16:20, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> A recent submission [1] from Rob has added additionalProperties: false
> to the interrupt-controller child node of RISC-V cpus, highlighting that
> the new cv1800b DT has been incorrectly using #address-cells.
> It has no child nodes, so #address-cells is not needed. Remove it.
>
> Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> CC: Chao Wei <chao.wei at sophgo.com>
> CC: Chen Wang <unicorn_wang at outlook.com>
> CC: Rob Herring <robh+dt at kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
> CC: Paul Walmsley <paul.walmsley at sifive.com>
> CC: Palmer Dabbelt <palmer at dabbelt.com>
> CC: Albert Ou <aou at eecs.berkeley.edu>
> CC: devicetree at vger.kernel.org
> CC: linux-riscv at lists.infradead.org
> CC: linux-kernel at vger.kernel.org
> ---
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..aec6401a467b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -34,7 +34,6 @@ cpu0: cpu at 0 {
>   			cpu0_intc: interrupt-controller {
>   				compatible = "riscv,cpu-intc";
>   				interrupt-controller;
> -				#address-cells = <0>;
>   				#interrupt-cells = <1>;
>   			};
>   		};

Acked-by: Chen Wang <unicorn_wang at outlook.com>

Thanks，btw, will it be merged in 6.7?

Looping Jisheng who is working on Duo/cv1800b.