[PATCH v4 0/7] Add Huashan Pi board support

[Conor Dooley]

Hey,

On Thu, Oct 19, 2023 at 07:18:00AM +0800, Inochi Amaoto wrote:
> Huashan Pi board is an embedded development platform based on the
> CV1812H chip. Add minimal device tree files for this board.
> Currently, it can boot to a basic shell.

Just pointing out that this series is too late for v6.7, so you probably
won't hear anything from me until v6.7-rc1 has been tagged.

Cheers,
Conor.

> 
> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
> 
> Link: https://en.sophgo.com/product/introduce/huashan.html
> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> Link: https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/
> 
> Changed from v3:
> 1. merge the patch 4 and 5 of v2 to preserve bisectability.
> 
> Changed from v2:
> 1. use dt override to save code.
> 2. code cleanup.
> 
> Changed from v1:
> 1. split the patch into several patch and refactor them.
> 
> Inochi Amaoto (7):
>   dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>   dt-bindings: timer: Add SOPHGO CV1812H clint
>   dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>   riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>   riscv: dts: sophgo: cv18xx: Add gpio devices
>   riscv: dts: sophgo: add initial CV1812H SoC device tree
>   riscv: dts: sophgo: add Huashan Pi board device tree
> 
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../devicetree/bindings/riscv/sophgo.yaml     |   4 +
>  .../bindings/timer/sifive,clint.yaml          |   1 +
>  arch/riscv/boot/dts/sophgo/Makefile           |   1 +
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi       | 119 +----------
>  .../boot/dts/sophgo/cv1812h-huashan-pi.dts    |  48 +++++
>  arch/riscv/boot/dts/sophgo/cv1812h.dtsi       |  24 +++
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi        | 193 ++++++++++++++++++
>  8 files changed, 279 insertions(+), 112 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> 
> --
> 2.42.0
> 
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