[PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties

[Yu-Chien Peter Lin]

On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote:
> Convert the RZ/Five devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> index b0796015e36b..eb301d8eb2b0 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -24,6 +24,9 @@ cpu0: cpu at 0 {
>  			reg = <0x0>;
>  			status = "okay";
>  			riscv,isa = "rv64imafdc";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";

We do have zihpm, and OpenSBI can also probe its existence.

Boot HART ISA Extensions  : zihpm
Boot HART MHPM Info       : 4 (0x00000078)

By the way, we will append "xandespmu" here.
I hope this is an appropriate way to add a new custom extension.

>  			mmu-type = "riscv,sv39";
>  			i-cache-size = <0x8000>;
>  			i-cache-line-size = <0x40>;