[GIT PULL] RISC-V Devicetrees for v6.6-final

[Conor Dooley]

Hey Arnd,

Just a single patch for you here, been quiet on the fixes front :)

Thanks,
Conor.

The following changes since commit 1558209533f140624a00408bdab796ab3f309450:

  riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order (2023-09-13 14:24:56 +0100)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-for-v6.6-final

for you to fetch changes up to cf98fe6b579e55aa71b6197e34c112b51f0c2a66:

  riscv: dts: starfive: visionfive 2: correct spi's ss pin (2023-10-12 10:23:23 +0100)

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RISC-V Devicetrees for v6.6-final

A single fix for the Starfive VisionFive 2 platform so that chip select
for SPI matches the vendor documentation.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

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Nam Cao (1):
      riscv: dts: starfive: visionfive 2: correct spi's ss pin

 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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