[PATCH v3 5/6] riscv: dts: allwinner: convert isa detection to new properties
Jernej Škrabec
jernej.skrabec at gmail.com
Fri Oct 13 12:22:28 PDT 2023
Dne ponedeljek, 09. oktober 2023 ob 11:37:49 CEST je Conor Dooley napisal(a):
> Convert the D1 devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Acked-by: Jernej Skrabec <jernej.skrabec at gmail.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
Applied, thanks!
Best regards,
Jernej
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 0856f18dc3cf..64c3c2e6cbe0 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -25,6 +25,9 @@ cpu0: cpu at 0 {
> mmu-type = "riscv,sv39";
> operating-points-v2 = <&opp_table_cpu>;
> riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> #cooling-cells = <2>;
>
> cpu0_intc: interrupt-controller {
>
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