[PATCH v1 07/13] dt-bindings: riscv: add Zfh/Zfhmin ISA extensions description

Conor Dooley conor at kernel.org
Thu Oct 12 06:49:07 PDT 2023


Yo,

On Wed, Oct 11, 2023 at 01:14:32PM +0200, Clément Léger wrote:
> Add description of Zfh and Zfhmin ISA extensions[1] which can now be
> reported through hwprobe for userspace usage.
> 
> [1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view
> 
Same here about using Link: tags.
Acked-by: Conor Dooley <conor.dooley at microchip.com>

Thanks,
Conor.

> Signed-off-by: Clément Léger <cleger at rivosinc.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml       | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 4002c65145c9..4c923800d751 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -190,6 +190,19 @@ properties:
>              instructions as ratified at commit 6d33919 ("Merge pull request #158
>              from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
>  
> +        - const: zfh
> +          description:
> +            The standard Zfh extension for 16-bit half-precision binary
> +            floating-point instructions, as ratified in commit 64074bc ("Update
> +            version numbers for Zfh/Zfinx") of riscv-isa-manual.
> +
> +        - const: zfhmin
> +          description:
> +            The standard Zfhmin extension which provides minimal support for
> +            16-bit half-precision binary floating-point instructions, as ratified
> +            in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
> +            riscv-isa-manual.
> +
>          - const: zicbom
>            description:
>              The standard Zicbom extension for base cache management operations as
> -- 
> 2.42.0
> 
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