[PATCH v5 00/10] Add Milk-V Pioneer RISC-V board support

[Chen Wang]

On 2023/10/7 20:36, Conor Dooley wrote:
> On Sat, Oct 07, 2023 at 08:25:55PM +0800, Chen Wang wrote:
>> On 2023/10/7 19:04, Conor Dooley wrote:
>>> On Sat, Oct 07, 2023 at 06:58:51PM +0800, Chen Wang wrote:
>>>> On 2023/10/7 18:17, Conor Dooley wrote:
>>>>> On Sat, Oct 07, 2023 at 03:52:04PM +0800, Chen Wang wrote:
>>>>>> From: Chen Wang <unicorn_wang at outlook.com>
>>>>>> Changes in v5:
>>>>>>      The patch series is based on v6.6-rc1. You can simply review or test
>>>>>>      the patches at the link [7].
>>>>>>      - dts: changed plic to support external interrupt
>>>>>>      - pickup improvements from Conor, details refer to [8].
>>>>> Did you? I only see them partially picked up. I'll just replace patch 8
>>>>> with the patch 8 from this series I think.
>>>> Yes, only the patch 8 of this series(v5) is updated for plic node. For other
>>>> patches, I just cherry-picked them from previous "sophon" branch.
>>> But added my signoff? I ended up seeing my signoff on the patch where I
>>> disagreed with the commit message, which was confusing to me.
>> Oh, I used to think I can keep the exising signoff and I didn't mean to add
>> it.
> I added mine when I applied the patches. It no longer makes sense when
> you resent another version.
>
>> Anyway, I agree your suggestion to create a new patch with only one
>> change should be better, I will follow this in later work.
> :)
>
>> Regarding your changes on sg2042 series, I have acked in another email : https://lore.kernel.org/linux-riscv/MA0P287MB0332BA73D0135CC73CAEA16DFEC8A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/.
>> If anything else required, please feel free let me know.
> An ack on Jisheng's series for the cv1800b would be nice.

Done, I have reviewed and acked all the files related to sophgo.