[PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC

[Conor Dooley]

On Mon, Nov 13, 2023 at 09:20:11PM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang at outlook.com>
> 
> Add clock generator node to device tree for SG2042, and enable clock for
> uart0.
> 
> Signed-off-by: Chen Wang <unicorn_wang at outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++

There's no need to create an entirely new file for this.

>  arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
>  2 files changed, 86 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
> new file mode 100644
> index 000000000000..66d2723fab35
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +/ {
> +	cgi: oscillator {
> +		compatible = "fixed-clock";
> +		clock-frequency = <25000000>;
> +		clock-output-names = "cgi";
> +		#clock-cells = <0>;
> +	};

What actually is this oscillator?
Is it provided by another clock controller on the SoC, or is it provided
by an oscillator on the board?

> +
> +	clkgen: clock-controller {
> +		compatible = "sophgo,sg2042-clkgen";
> +		#clock-cells = <1>;
> +		system-ctrl = <&sys_ctrl>;

Why is this node not a child of the system controller?

Cheers,
Conor.
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