[PATCH 1/2] perf tools riscv: Allow get_cpuid return empty MARCH and MIMP

[Nikita Shubin]

On Tue, 2023-05-16 at 17:43 +0800, Inochi Amaoto wrote:
> > > The T-HEAD C9xx series CPU only has MVENDOR defined, and left
> > > MARCH
> > > and MIMP unimplemented.
> > 
> > According to the docs you can still read them, but it's hardwired
> > to
> > 64h0.
> > 
> > How it's supposed to distinguish c906 and c910 for example ?
> 
> It is unnecessary to distinguish c9xx, their event index is
> compatible.
> The dtb and opensbi will final decide which event can be used.
> 
> > What does /proc/cpuinfo shows on c9xx ? Why can't we use zeroes ?
> 
> The content is as follows.
> 
> processor     : 0
> hart          : 0
> isa           : rv64imafdc
> mmu           : sv39
> uarch         : thead,c910
> mvendorid     : 0x5b7
> marchid       : 0x0
> mimpid        : 0x0

Then why do you need first patch then ?

marchid, mimpid will never be NULL they "0x0" and "0x0" strings
respectively.

How have you tested it ? 

There no way "0x5b7-0x0000000000000000-0x[[:xdigit:]]+" will match
"0x5b7-0x0-0x0" which cpuid in your case.

Just drop this patch.

Anyway "PAGER=cat perf list pmu" gives me an empty list on licheerv.

> 
> The `mvendorid`, `marchid`, `mimpid` are the same across allwinner D1
> (C906),
> T-HEAD th1520 (C910) and the sophgo mango (C920). It seems T-HEAD use
> MCPUID
> CSR to store CPU info. But this is not standard and not shown in
> cpuinfo.
> 
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