[PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree

[Conor Dooley]

On Wed, Mar 22, 2023 at 10:02:40PM +0000, Conor Dooley wrote:
> On Mon, Mar 20, 2023 at 06:37:48PM +0800, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel at esmil.dk>
> > 
> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
> > Technology Ltd.
> > 
> > Tested-by: Tommaso Merciai <tomm.merciai at gmail.com>
> > Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> > Signed-off-by: Emil Renner Berthing <kernel at esmil.dk>
> > Co-developed-by: Jianlong Huang <jianlong.huang at starfivetech.com>
> > Signed-off-by: Jianlong Huang <jianlong.huang at starfivetech.com>
> > Co-developed-by: Hal Feng <hal.feng at starfivetech.com>
> > Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> > ---
> 
> > +		S7_0: cpu at 0 {
> > +			compatible = "sifive,s7", "riscv";
> > +			reg = <0>;
> > +			d-cache-block-size = <64>;
> > +			d-cache-sets = <64>;
> > +			d-cache-size = <8192>;
> > +			d-tlb-sets = <1>;
> > +			d-tlb-size = <40>;
> > +			device_type = "cpu";
> > +			i-cache-block-size = <64>;
> > +			i-cache-sets = <64>;
> > +			i-cache-size = <16384>;
> > +			i-tlb-sets = <1>;
> > +			i-tlb-size = <40>;
> > +			mmu-type = "riscv,sv39";
> > +			next-level-cache = <&ccache>;
> > +			riscv,isa = "rv64imac_zba_zbb";
> > +			tlb-split;
> > +			status = "disabled";
> 
> Jess pointed out on IRC that this S7 entry looks wrong as it is claiming
> that the S7 has an mmu. I didn't go looking back in the history of
> u74-mc core complex manuals, but the latest version does not show an mmu
> for the S7.

BTW Hal, if the dt-binding stuff is okay with Emil, I can just remove
the mmu here if you confirm it is a mistake rather than you needing to
resubmit to remove it.

Cheers,
Conor.
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