[PATCH -next v15 09/19] riscv: Add task switch support for vector

[Conor Dooley]

On Fri, Mar 17, 2023 at 11:35:28AM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu at sifive.com>
> 
> This patch adds task switch support for vector. It also supports all
> lengths of vlen.
> 
> Suggested-by: Andrew Waterman <andrew at sifive.com>
> Co-developed-by: Nick Knight <nick.knight at sifive.com>
> Signed-off-by: Nick Knight <nick.knight at sifive.com>
> Co-developed-by: Guo Ren <guoren at linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
> Co-developed-by: Vincent Chen <vincent.chen at sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen at sifive.com>
> Co-developed-by: Ruinland Tsai <ruinland.tsai at sifive.com>
> Signed-off-by: Ruinland Tsai <ruinland.tsai at sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
> Signed-off-by: Vineet Gupta <vineetg at rivosinc.com>
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>

> @@ -131,6 +166,9 @@ static __always_inline bool has_vector(void) { return false; }
>  static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
>  #define riscv_v_vsize (0)
>  #define riscv_v_setup_vsize()	 		do {} while (0)
                                        ^
vim complains that you added a space here, between the first and second
tabs.

Otherwise,
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

Thanks,
Conor.

> +#define riscv_v_vstate_save(task, regs)		do {} while (0)
> +#define riscv_v_vstate_restore(task, regs)	do {} while (0)
> +#define __switch_to_vector(__prev, __next)	do {} while (0)
>  #define riscv_v_vstate_off(regs)		do {} while (0)
>  #define riscv_v_vstate_on(regs)			do {} while (0)
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