[RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Krzysztof Kozlowski]

On 20/03/2023 06:54, William Qiu wrote:
> 
> 
> On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
>> On 15/03/2023 06:58, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <william.qiu at starfivetech.com>
>>> ---
>>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>>>  MAINTAINERS                                   |  5 +++
>>>  2 files changed, 46 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> new file mode 100644
>>> index 000000000000..ae7f1d6916af
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> @@ -0,0 +1,41 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive JH7110 SoC system controller
>>> +
>>> +maintainers:
>>> +  - William Qiu <william.qiu at starfivetech.com>
>>> +
>>> +description: |
>>> +  The StarFive JH7110 SoC system controller provides register information such
>>> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - enum:
>>> +          - starfive,jh7110-aon-syscon
>>> +          - starfive,jh7110-stg-syscon
>>> +          - starfive,jh7110-sys-syscon
>>> +      - const: syscon
>>
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>> ... or your PLL clock controller was not tested.
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
> 
> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
> was not tested which I didn't add in this patch series. And PLL clock controller belongs
> to Xingyu Wu, I would tell him.

What's confusing you do not allow here clock controller.

Best regards,
Krzysztof