[PATCH v3 00/11] Add new partial clock and reset drivers for StarFive JH7110

[Xingyu Wu]

On 2023/3/15 8:30, Stephen Boyd wrote:
> Quoting Xingyu Wu (2023-03-14 05:43:53)
>> This patch serises are to add new partial clock drivers and reset
>> supports about System-Top-Group(STG), Image-Signal-Process(ISP)
>> and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC.
> 
> What is your merge plan for this series? Did you intend for clk tree to
> take the majority of patches? We won't take the dts changes through the
> clk tree.
> 
> I think Philipp Zabel reviewed some earlier version of the patches and
> provided reviewed-by tags. Can you check if they can be added here? If
> so, please resend again, or get those merged through the reset tree.

These patches add new clock & reset providers based on the basic clock & reset
of the minimal system which Hal.feng had submitted[1], which are used in USB, DMA,
VIN and Display modules that are merging.
[1]: https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/

Oh I checked and had not received any comments from Philipp Zabel in earlier version
of these patches. Maybe it was confused with the patches of the minimal system.

Best regards,
Xingyu Wu