[PATCH v5 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2
Palmer Dabbelt
palmer at rivosinc.com
Tue Mar 14 18:45:18 PDT 2023
On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho at starfivetech.com wrote:
> Adding StarFive TRNG controller node to VisionFive 2 SoC.
>
> Co-developed-by: Jenny Zhang <jenny.zhang at starfivetech.com>
> Signed-off-by: Jenny Zhang <jenny.zhang at starfivetech.com>
> Signed-off-by: Jia Jie Ho <jiajie.ho at starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 4ac159d79d66..3c29e0bc6246 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -455,5 +455,15 @@ uart5: serial at 12020000 {
> reg-shift = <2>;
> status = "disabled";
> };
> +
> + rng: rng at 1600c000 {
> + compatible = "starfive,jh7110-trng";
> + reg = <0x0 0x1600C000 0x0 0x4000>;
> + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
> + clock-names = "hclk", "ahb";
> + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> + interrupts = <30>;
> + };
> };
> };
Acked-by: Palmer Dabbelt <palmer at rivosinc.com>
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