[PATCH v5 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Hal Feng
hal.feng at starfivetech.com
Sun Mar 12 20:22:31 PDT 2023
On Sat, 11 Mar 2023 13:11:38 +0000, Conor Dooley wrote:
> On Sat, Mar 11, 2023 at 05:07:23PM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel at esmil.dk>
>>
>> Add bindings for the system clock and reset generator (SYSCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel at esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
>> ---
>> .../clock/starfive,jh7110-syscrg.yaml | 104 +++++++++
>> MAINTAINERS | 8 +-
>> .../dt-bindings/clock/starfive,jh7110-crg.h | 203 ++++++++++++++++++
>> .../dt-bindings/reset/starfive,jh7110-crg.h | 142 ++++++++++++
>> 4 files changed, 454 insertions(+), 3 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
>> create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> new file mode 100644
>> index 000000000000..84373ae31644
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>
>> + clock-names:
>> + oneOf:
>> + - items:
>> + - const: osc
>> + - enum:
>> + - gmac1_rmii_refin
>> + - gmac1_rgmii_rxin
>> + - const: i2stx_bclk_ext
>> + - const: i2stx_lrck_ext
>> + - const: i2srx_bclk_ext
>> + - const: i2srx_lrck_ext
>> + - const: tdm_ext
>> + - const: mclk_ext
>> +
>> + - items:
>> + - const: osc
>> + - const: gmac1_rmii_refin
>> + - const: gmac1_rgmii_rxin
>> + - const: i2stx_bclk_ext
>> + - const: i2stx_lrck_ext
>> + - const: i2srx_bclk_ext
>> + - const: i2srx_lrck_ext
>> + - const: tdm_ext
>> + - const: mclk_ext
>
> Assuming nothing else here is optional,
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
Yeah, nothing else here is optional. Thanks for your review.
Best regards,
Hal
More information about the linux-riscv
mailing list