[PATCH 0/2] riscv: asid: switch to alternative way to fix stale TLB entries

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer at rivosinc.com>:

On Sun, 26 Feb 2023 18:01:35 +0300 you wrote:
> Hi all,
> 
> Some time ago two different patches have been posted to fix stale TLB
> entries that caused applications crashes.
> 
> The patch [0] suggested 'aggregating' mm_cpumask, i.e. current cpu is not
> cleared for the switched-out task in switch_mm function. For additional
> explanations see the commit message by Guo Ren. The same approach is
> used by arc architecture, so another good comment is for switch_mm
> in arch/arc/include/asm/mmu_context.h.
> 
> [...]

Here is the summary with links:
  - [1/2] Revert "riscv: mm: notify remote harts about mmu cache updates"
    https://git.kernel.org/riscv/c/e921050022f1
  - [2/2] riscv: asid: Fixup stale TLB entry cause application crash
    https://git.kernel.org/riscv/c/82dd33fde026

You are awesome, thank you!
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