[PATCH] Revert "riscv: Set more data to cacheinfo"

[Song Shuai]

Hi, Conor & Sudeep :

Sudeep Holla <sudeep.holla at arm.com> 于2023年3月8日周三 11:35写道：
>
> On Wed, Mar 08, 2023 at 02:47:34PM +0800, Song Shuai wrote:
> > This reverts commit baf7cbd94b5688f167443a2cc3dcea3300132099.
> >
> > There are some duplicate cache attributes populations executed
> > in both ci_leaf_init() and later cache_setup_properties().
> >
> > Revert the commit baf7cbd94b56 ("riscv: Set more data to cacheinfo")
> > to setup only the level and type attributes at this early place.
> >
>
> I had noticed the same and had something similar when we did some rework
> around for v6.1 merge window. But there were lot of other issues to be
> addressed at the moment and hence deferred this.
>
> So for the change in general, but as Conor responded, it would be good
> to do some checking to ensure nothing breaks and all the requirements
> this patch(baf7cbd94b56) addressed are already handled in the core.

As you suggested, commit (da29dbcda49d "riscv: Add cache information
in AUX vector")
in the "Get cache information from userland" series should be checked.

The commit da29dbcda49d adds the cacheinfo (read from
ci_cacheinfo(cpu)) in ELF auxiliary vectors,
so process can fetch the cacheinfo through glibc sysconf() after ELF loading.
At the same time, the glibc related support was enabled by its commit
(15b38ffc10 "riscv: Get cache information through sysconf")

With this reverting patch applied, the output of `getconf -a` looks good
in Qemu sifive_u machine and rootfs image with glibc-2.35.

```
LEVEL1_ICACHE_SIZE 32768
LEVEL1_ICACHE_ASSOC 8
LEVEL1_ICACHE_LINESIZE 64
LEVEL1_DCACHE_SIZE 32768
LEVEL1_DCACHE_ASSOC 8
LEVEL1_DCACHE_LINESIZE 64
LEVEL2_CACHE_SIZE 2097152
LEVEL2_CACHE_ASSOC 32
LEVEL2_CACHE_LINESIZE 64
```

>
> Acked-by: Sudeep Holla <sudeep.holla at arm.com>
>
> --
> Regards,
> Sudeep



-- 
Thanks,
Song