[PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC

[Conor Dooley]

On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote:
> On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:

> > The above two methods can fix the problem. Here are my test results.
> > The VisionFive board can boot up successfully if and only if all above
> > two applied.
> > The VisionFive 2 board can boot up successfully if I merge Linus's new
> > changes.
> 
> Tested also on my side. Hope this can be helpfull.
> 
> > Hope your fix will be merged in rc2. Thank you for your reply.
> 
> Fully agree.

If you only have a VisionFive 2, it shouldn't matter to you, as you
don't need to fix up any SiFive errata (at the moment at least).
Linus' fix is already in his tree, so should be in -rc2!
The fix for the VisionFive was applied to Palmer's RISC-V fixes tree
last night:
https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b

Thanks,
Conor.
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