[PATCH v1] RISC-V: Add basic support for the vector extension

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

I've started hitting this in CI while testing Andy's vector enablement
series. I'm not entirely sure if there is more to do here, other than
squeezing in the duplicate of what has been done for other extensions.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
This is based on top of patches already on the sparse list, adding
support for some multi-letter extensions for RISC-V:
https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/
https://lore.kernel.org/linux-sparse/20220811052957.16634-1-palmer@rivosinc.com/

CC: luc.vanoostenryck at gmail.com
CC: palmer at dabbelt.com
CC: linux-sparse at vger.kernel.org
CC: linux-riscv at lists.infradead.org
---
 target-riscv.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-riscv.c b/target-riscv.c
index 8338d7a6..c8282814 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -21,6 +21,7 @@
 #define RISCV_ZIFENCEI		(1 << 11)
 #define RISCV_ZICBOM		(1 << 12)
 #define RISCV_ZIHINTPAUSE	(1 << 13)
+#define RISCV_VECTOR		(1 << 14)
 
 static unsigned int riscv_flags;
 
@@ -41,6 +42,7 @@ static void parse_march_riscv(const char *arg)
 		{ "f",			RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR },
 		{ "d",			RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR },
 		{ "c",			RISCV_COMP },
+		{ "v",			RISCV_VECTOR },
 		{ "_zicsr",		RISCV_ZICSR },
 		{ "_zifencei",		RISCV_ZIFENCEI },
 		{ "_zicbom",		RISCV_ZICBOM },
@@ -147,6 +149,8 @@ static void predefine_riscv(const struct target *self)
 		predefine("__riscv_zicbom", 1, "1");
 	if (riscv_flags & RISCV_ZIHINTPAUSE)
 		predefine("__riscv_zihintpause", 1, "1");
+	if (riscv_flags & RISCV_VECTOR)
+		predefine("__riscv_vector", 1, "1");
 
 	if (cmodel)
 		predefine_strong("__riscv_cmodel_%s", cmodel);
-- 
2.39.2